{"id":56,"date":"2018-02-19T12:36:14","date_gmt":"2018-02-19T16:36:14","guid":{"rendered":"https:\/\/sites.bu.edu\/mark\/?page_id=56"},"modified":"2024-05-08T16:14:12","modified_gmt":"2024-05-08T20:14:12","slug":"resume","status":"publish","type":"page","link":"https:\/\/sites.bu.edu\/mark\/resume\/","title":{"rendered":"Resume"},"content":{"rendered":"

<\/strong><\/p>\n

Mark Karpovsky<\/strong>
\nProfessor Emeritus
\nBoston University. Department of Electrical and Computer Engineering
\nE-mail: markkar@bu.edu<\/p>\n

\n

Education:<\/strong>
\nPh.D. <\/strong>Department<\/span>\u00a0<\/span>of Mathematics,\u00a0 Leningrad<\/span>\u00a0<\/span>Electrotechnical<\/span>\u00a0<\/span>Institute, Leningrad, USSR.
\nM.S.<\/strong>\u00a0<\/span>Department of Computer Science,\u00a0 Leningrad<\/span>\u00a0<\/span>Electrotechnical<\/span>\u00a0<\/span>Institute, Leningrad, USSR.
\nB.S.<\/strong>\u00a0<\/span>Department of Computer Science,\u00a0 Leningrad<\/span>\u00a0<\/span>Electrotechnical<\/span>\u00a0<\/span>Institute, Leningrad, USSR.<\/p>\n

\n

Employment:<\/strong><\/p>\n

June 2002- July. 2002<\/strong>, Visiting Professor, Tampere International Center for Signal Processing. Finland.<\/p>\n

June 2000- July<\/strong>,\u00a0<\/span>2000<\/strong>, Visiting Professor, Tampere International Center for Signal Processing, Finland.<\/p>\n

Feb 1997 – Mar. 1997<\/strong>\u00a0<\/span>Visiting Professor, Department of Electrical and Computer Engineering, New Jersey Institute of Technology.<\/p>\n

June 1990 – July 1990<\/strong>\u00a0<\/span>Visiting Professor, Department of Computer Science, University of Dortmund, Dortmund, Germany.<\/p>\n

May 1990 – June 1990<\/strong>\u00a0<\/span>Visiting Professor, Department of Computer Science,\u00a0<\/span>Ecole<\/span>\u00a0<\/span>National\u00a0<\/span>Superieure<\/span>\u00a0<\/span>des Telecommunication, Paris, France.<\/p>\n

1983 – Present<\/strong>\u00a0<\/span>Professor, Department of Electrical, Computers and Systems Engineering, Boston University, Boston, MA 02215.<\/p>\n

1987 – Present<\/strong>\u00a0<\/span>Director, Reliable Computing Laboratory, Boston University,\u00a0<\/span>Boston<\/span>, MA 02215.<\/p>\n

1989<\/strong>\u00a0<\/span>Consultant for ATT Bell Laboratories, Andover, MA.<\/p>\n

1987<\/strong>\u00a0<\/span>Consultant for Standard\u00a0<\/span>Electrik<\/span>\u00a0<\/span>Corporation, Germany<\/p>\n

1986<\/strong>\u00a0<\/span>Consultant for Honeywell Corporation, Billerica, MA.<\/p>\n

1984 – 1985\u00a0<\/span><\/strong>Consultant for Digital Equipment Corporation, Maynard, MA.<\/p>\n

1982 – 1983<\/strong>\u00a0<\/span>Professor, Computer Science Department, State University of New York, Binghamton, NY.<\/p>\n

1981 – 1983<\/strong>\u00a0<\/span>Consultant for IBM Corporation, Endicott, NY.<\/p>\n

May 1983 – June 1983<\/strong>\u00a0<\/span>Visiting Professor, Department of Computer Science,\u00a0<\/span>Ecole<\/span>\u00a0<\/span>National\u00a0<\/span>Superieure<\/span>\u00a0<\/span>des Telecommunication, Paris, France.<\/p>\n

1978 – 1982<\/strong>\u00a0<\/span>Associate Professor, Coordinator of Research and Ph.D. Program, Computer Science Department, State University of New York at Binghamton, NY.<\/p>\n

May 1982 – June 1982<\/strong>\u00a0<\/span>Visiting Professor , Department of Computer Science,\u00a0<\/span>Ecole<\/span>\u00a0<\/span>National\u00a0<\/span>Superieure<\/span>\u00a0<\/span>des Telecommunication, Paris, France.<\/p>\n

1976 – 1977<\/strong>\u00a0<\/span>Head of Computer Science Division, Department of Mathematics, Tel Aviv, Israel.<\/p>\n

1973 – 1978<\/strong>\u00a0<\/span>Senior Lecturer, Department of Mathematics, Computer Science Division, Tel Aviv University, Tel Aviv, Israel.<\/p>\n

1968 – 1971<\/strong>\u00a0<\/span>Consultant,\u00a0<\/span>The<\/span>\u00a0<\/span>Military Scientific Research Institute, Leningrad, USSR.<\/p>\n

1967<\/strong>\u00a0<\/span>Engineer,\u00a0<\/span>The<\/span>\u00a0<\/span>Scientific Research Institute, Leningrad, USSR.<\/p>\n

1964 – 1966<\/strong>\u00a0<\/span>Junior Research Worker,\u00a0<\/span>The<\/span>\u00a0<\/span>Leningrad\u00a0<\/span>Electrotechnical<\/span>\u00a0<\/span>Institute, Leningrad, USSR.<\/p>\n

January 1963 – December 1963<\/strong>\u00a0<\/span>Engineer, Scientific Research Institute, Leningrad, USSR.<\/p>\n

1958 – 1962<\/strong>\u00a0<\/span>Laboratory Asst.,\u00a0<\/span>The<\/span>\u00a0<\/span>Department of Electronic Computers, Leningrad\u00a0<\/span>Electrotechnical<\/span>\u00a0<\/span>Institute, Leningrad, USSR.<\/p>\n

\n

Professional Societies, Citations and Committee Membership:<\/strong><\/p>\n

Nokia Foundation Visiting Fellowship, 2005<\/p>\n

Institute of Electrical and Electronic Engineers, Fellow.<\/p>\n

International\u00a0<\/span>Informatization<\/span>\u00a0<\/span>Academy, Associate Member.<\/p>\n

Who is\u00a0<\/span>Who<\/span>\u00a0<\/span>in the World.<\/p>\n

New York Academy of Science, Member.<\/p>\n

American Society of Engineering Education, Member.<\/p>\n

Main Advisor for 20 doctoral students in USSR, Israel, SUNY-Binghamton and Boston University.<\/p>\n

Editorial Advisory Board, open access in computer science,\u00a0<\/span>Verista<\/span>, Member<\/p>\n

\n

Patents.
\n<\/strong>
\n1. Mark Karpovsky, Alexander Taubin, Konrad Kulikowski,\u00a0<\/span>
\nSystem employing systematic robust error detection coding to protect system element against errors with unknown probability distributions<\/a>
\nPublication number\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0<\/span>US20070019805 A1
\n<\/em>Publication type\u00a0\u00a0\u00a0<\/span>Application<\/p>\n

    \n
  1. Hans J. Matt, Mark G. Karpovsky, Lev B. Levitin,
    \n    Method of testing connecting and\/or switching devices and\/or lines<\/a>
    \nPublication number<\/span>US5134618 A
    \n<\/em>Publication type\u00a0\u00a0\u00a0<\/span>Grant<\/li>\n<\/ol>\n
    \n

    Inventions<\/strong><\/p>\n

    1. M.G. Karpovsky, V. S.\u00a0<\/span>Tolstiakov<\/span>, V. N.\u00a0<\/span>Nomokonov<\/span>, I. L.\u00a0<\/span>Erosh<\/span>, Certificate of Authorship No. 18177<\/em>\u00a0<\/span>for the invention: “A Method for Error-Correction in Binary Counters,” USSR, April 1965 (Russian).<\/p>\n

    2. M.G. Karpovsky, V. S.\u00a0<\/span>Tolstiakov<\/span>, V. N.\u00a0<\/span>Nomokonov<\/span>, I. L.\u00a0<\/span>Erosh<\/span>,\u00a0<\/span>Certificate of Authorship No. 207888<\/em>\u00a0<\/span>for the invention: “Accumulation Counter with Magnetic Elements,” USSR, May 1965 (Russian).<\/p>\n

    3. M.G. Karpovsky, V. S.\u00a0<\/span>Tolstiakov<\/span>, V. N.\u00a0<\/span>Nomokonov<\/span>, I. L.\u00a0<\/span>Erosh<\/span>,\u00a0<\/span>Certificate of Authorship No. 217456<\/em>\u00a0<\/span>for the invention: “Pulsed Counter with Error Detection and Error Correction,” USSR, June 1966 (Russian).<\/p>\n

    4. M.G. Karpovsky, V. S.\u00a0<\/span>Tolstiakov<\/span>, V. N.\u00a0<\/span>Nomokonov<\/span>, I. L.\u00a0<\/span>Erosh<\/span>,\u00a0<\/span>Certificate of Authorship No. 2354242<\/em>\u00a0<\/span>for the invention: “Self-Correcting Flip-Flop Using “NOR” Potential Elements and Pulse Input,” USSR, July 1967 (Russian).<\/p>\n

    \n

    Proceedings<\/strong><\/p>\n

    5. M.G. Karpovsky, “Synthesis of Digital Devices with the Required Error Correcting Capability<\/a>,”\u00a0<\/span>Proc. Leningrad\u00a0<\/span>Elecrotechnical<\/span>\u00a0<\/span>Institute<\/em>, No.65, part. 2, 1968 (Russian).<\/p>\n

    6. M.G. Karpovsky, B. I.\u00a0<\/span>Ruzansky<\/span>, V. S.\u00a0<\/span>Tcherbakov<\/span>, “Synthesis of Fault Tolerant Finite Automata<\/a>“\u00a0<\/span>Proc., Third Conference on Theory of Transmission and Coding of Information, part 3,<\/em>\u00a0<\/span>Moscow, USSR.<\/p>\n

    7. M.G. Karpovsky, E. S.\u00a0<\/span>Moskalev<\/span>, V. V.\u00a0<\/span>Danilov<\/span>, “Estimations on the Number of Tests for Orientated Graphs<\/a>,”\u00a0<\/span>Proc. Leningrad\u00a0<\/span>Electrotechnical<\/span>\u00a0<\/span>Institute<\/em>, No. 68, 1968 (Russian).<\/p>\n

    8. M.G. Karpovsky, E. S.\u00a0<\/span>Moskalev<\/span>, “One Method of State Assignment for Finite Automata<\/a>,”\u00a0<\/span>Proc. Second Conference on Theory of Transmission and Coding of Information<\/em>, part 3, Moscow, USSR, 1968 (Russian).<\/p>\n

    9. M.G. Karpovsky, V. V.\u00a0<\/span>Dnilov<\/span>, E. S.\u00a0<\/span>Moskalev<\/span>, “Optimization of Coverings used for the Construction of Tests<\/a>,”\u00a0<\/span>Proc. Leningrad\u00a0<\/span>Electrotechnical<\/span>\u00a0<\/span>Institute<\/em>, No. 84, 1969 (Russian).<\/p>\n

    10. M.G. Karpovsky, A. A.\u00a0<\/span>Troianovsky<\/span>, “One method of Reducing Redundancy for Sequential Machines with Error Correction<\/a>,”\u00a0<\/span>Proc. First Symposium on Synthesis Fault-Tolerant Automata<\/em>, Kiev, 1971 (Russian).<\/p>\n

    11. M.G. Karpovsky, A. A.\u00a0<\/span>Troianovsky<\/span>, “Analysis of the Error Correcting Capability for Finite Automata<\/a>,”\u00a0<\/span>Proc. Fifth Symposium on Using Redundancy in Information Systems<\/em>, Leningrad, USSR, 1972 (Russian).<\/p>\n

    12. M.G. Karpovsky, E. S.\u00a0<\/span>Moskalev<\/span>, A. A.\u00a0<\/span>Troianovsky<\/span>, “Analysis of the Correcting Power for Logical Functions<\/a>,”\u00a0<\/span>Proc. Fifth Symposium on Using Redundancy in Information Systems<\/em>, Leningrad, USSR, 1972 (Russian).<\/p>\n

    13. M.G. Karpovsky, A. A.\u00a0<\/span>Troianovsky<\/span>, “State Assignment Method for Non-Redundant Automata with Error Correction<\/a>,”\u00a0<\/span>Proc. Fifth Symposium on Using Redundancy in Information Systems<\/em>, Leningrad, USSR, 1972 (Russian).<\/p>\n

    14. M.G. Karpovsky, E. A. Trachtenberg, “Circulants in Finite Groups<\/a><\/span>,”\u00a0<\/span>Technical Report No. 67<\/em>, Israel, December 1975.<\/p>\n

    15. M.G. Karpovsky, “On Covering Radius of (n,k<\/span>) codes<\/a>,”\u00a0<\/span>Proc. of International Symposium on Information Theory<\/em>, Les Arcs, France, June 1982.<\/p>\n

    16. M.G. Karpovsky, L.B. Levitin, “Error Detection in Combinational Network by Use of Codes Based on\u00a0<\/span>Hadamard<\/span>\u00a0<\/span>Matrices<\/a>,”\u00a0<\/span>Proc. of International Symposium on Information Theory<\/em>, St.\u00a0<\/span>Jovite<\/span>, Canada, 1983.<\/p>\n

    17. M.G. Karpovsky, L.B. Levitin, “A new Probabilistic Approach to VLSI Circuits Testing<\/a>,”\u00a0<\/span>International Workshop on Fault-Detection and Spectral Techniques<\/em>, October 1983, Boston, pp. 3.1-3.34.<\/p>\n

    18. L. Trachtenberg, M. G. Karpovsky, “Detection of Signals in Communication Channels by Fourier Transforms Over Finite Groups<\/a>,”\u00a0<\/span>International Workshop on Fault-Detection and Spectral Techniques<\/em>, October 1983, Boston, pp. 9.1 – 9.15.<\/p>\n

    19. P.\u00a0<\/span>Frankl<\/span>, M. G. Karpovsky, L. B. Levitin, “Exhaustive Testing of Almost all Devices with Output Depending on Limited Number of Inputs<\/a>,”\u00a0<\/span>International Symposium on Information Theory<\/em>, Brighton, United Kingdom, 1985.<\/p>\n

    20. L. B. Levitin, M. G. Karpovsky, “Efficient Tests Based on MDS Codes<\/a>,”\u00a0<\/span>International Symposium on Information Theory<\/em>, Ann Arbor, MI, 1986.<\/p>\n

    21. M.G. Karpovsky, P.\u00a0<\/span>Nagvajara<\/span>, “Asymptotically Bent Functions and Optimal Quadratic Codes for the\u00a0<\/span>Minimax<\/span>\u00a0<\/span>Criterion on Error-Detection<\/a>,”\u00a0<\/span>Proc. International Symposium on Information Theory<\/em>, Japan, 1988.<\/p>\n

    22. L.B. Levitin, M. G. Karpovsky, P.\u00a0<\/span>Frankl<\/span>, “Exhaustive Testing of Almost All Devices with Outputs Depending on Limited Number of Inputs,”\u00a0<\/span>Proc. of Sixth International Symposium on Networks, Systems and Signal Processing<\/em>, Zagreb, Yugoslavia, 1989.<\/p>\n

    23. M. G. Karpovsky, L. B. Levitin, F. S.\u00a0<\/span>Vainstein<\/span>, “Hard and Soft Decisions in Diagnosis by Space-Time Signatures<\/a>,”\u00a0<\/span>Proc. of International Symposium on Information Theory<\/em>, Budapest, Hungary, 1991.<\/p>\n

    24. L. B. Levitin, M. G. Karpovsky, “Traveling Salesman Problem in the Space of Binary Vectors<\/a>,”\u00a0<\/span>Proc. of International Symposium on Information\u00a0<\/span>Theory\u00a0,<\/span><\/em>\u00a0<\/span>Norway, 1994.<\/p>\n

    25. M. G. Karpovsky, “New Techniques in Testing and Diagnosis of Computer Hardware,” Keynote paper,\u00a0<\/span>North Atlantic Test Workshop<\/em>, 1998.<\/p>\n

    \n

    Monographs, Books<\/strong><\/p>\n

    26. M. G. Karpovsky, “Mathematical Methods of Synthesis of Switching Circuits with Error Detection and Error Correction<\/em>,” Ph. D. Dissertation, Leningrad\u00a0<\/span>Electrotechnical<\/span>\u00a0<\/span>Institute, Leningrad, USSR, 1967 (Russian).<\/p>\n

    27. M. G. Karpovsky, E. S.\u00a0<\/span>Moskalev<\/span>, “Spectral Methods of Analysis and Synthesis of Switching Circuits<\/em>,” Energy, Leningrad, USSR, 1972 (Russian).<\/p>\n

    28. M. G. Karpovsky, “Finite Orthogonal Series in the Design of Digital Devices<\/em>,” John Wiley, New York, 1976.<\/p>\n

    29. M. G. Karpovsky (Editor), “Spectral Techniques and Fault Detection<\/a><\/em>,” Academic Press, 1985.<\/p>\n

      \n
    1. M. G. Karpovsky, R.S. Stankovic, J. T. Astola,<\/span>“Spectral Logic and Its Applications for the Design of Digital Devices”,<\/em><\/span>John\u00a0<\/span>Wiley&Sons<\/span>, 595 pages, ,<\/span>\u00a0<\/span>2008.
      \n><\/li>\n<\/ol>\n
      \n

      Chapters in Books<\/strong><\/p>\n

      30. M. G. Karpovsky, “Synthesis of Digital Services with Error Detection and Error Correction” in\u00a0<\/span>Soviet Radio<\/em>, Chapters 4-6 (Russian).<\/p>\n

      32. M. G. Karpovsky, V. V.\u00a0<\/span>Danilov<\/span>, E. S.\u00a0<\/span>Moskalev<\/span>, “Tests for Digital Devices<\/a>” in\u00a0<\/span>Monograph:Technical<\/em><\/span>\u00a0<\/span>Diagnosis<\/em>, Prof.\u00a0<\/span>Parkhomenko<\/span>\u00a0<\/span>Ed., Moscow, 1972 (Russian).<\/p>\n

      33. M. G. Karpovsky, G. S.\u00a0<\/span>Kan<\/span>, I. I.\u00a0<\/span>Sisoev<\/span>, A. A.\u00a0<\/span>Troianovsky<\/span>., Yu. A.\u00a0<\/span>Shapkov<\/span>, “Mathematical Model for Activity of the Muscles in Maintaining the Upright Position of a Human Being” in Monograph:\u00a0<\/span>Some Problems of Biological Cybernetics<\/em>, Acad. Berg Ed., 1972 (Russian).<\/p>\n

      34. M. G. Karpovsky, E. A. Trachtenberg, “Detection of signals in Communication Channels by Fourier Transforms over Finite Groups<\/em>,”\u00a0<\/span>in Spectral Techniques and Fault Detection<\/em>, M. G. Karpovsky, editor, Academic Press, 1985.<\/p>\n

      35. M. G. Karpovsky, L. B. Levitin, “Universal Testing of Computer Hardware<\/a>,” In\u00a0<\/span>Spectral Techniques and Fault Detection<\/em>, M. G. Karpovsky, Editor, Academic Press, 1985.<\/p>\n

      \n

      Articles<\/strong>\u00a0<\/span><\/strong>(Book reviews, short notes and research reports not listed)<\/span><\/p>\n

      36. M. G. Karpovsky, E.S.\u00a0<\/span>Moskalev<\/span>, B.S.\u00a0<\/span>Podkletnov<\/span>, “One Method of Synthesis of Logical Networks,”\u00a0<\/span>Problems of\u00a0<\/span>Radioelectronics<\/span><\/em>, No.12, 1966 (Russian).<\/p>\n

      37. M. G. Karpovsky, E.S.\u00a0<\/span>Moskalev<\/span>, “Realization of System of Logical Functions by Means of an Expansion in Orthogonal Series<\/a>,”\u00a0<\/span>Automata.\u00a0<\/span>and<\/span>\u00a0<\/span>Remote Control<\/em>, Vol.28, N. 23, pp. 1921-1932, December 1967.<\/p>\n

      38. M. G. Karpovsky, V.N.\u00a0<\/span>Nomokonov<\/span>, “Synthesis of Logical Networks for Redundant State Assignment of Binary Counters<\/a>,”\u00a0<\/span>Problems of\u00a0<\/span>Radioelectronics<\/span><\/em>, No. 27, 1968 (Russian).<\/p>\n

      39. M. G. Karpovsky, B.S.\u00a0<\/span>Levit<\/span>, B.E.\u00a0<\/span>Ruzansky<\/span>, “Algorithms for State Assignment and Minimization for Finite Automata with Error Correction<\/a>,”\u00a0<\/span>Methods of Computations<\/em>, No. 5, 1968 (Russian).<\/p>\n

      40. M. G. Karpovsky, “Sequential Machines with Error Detection and Error Correction<\/a>,”\u00a0<\/span>Computer Science and Problems of Cybernetics<\/em>, No. 5, 1968 (Russian).<\/p>\n

      41. M. G. Karpovsky, E.S.\u00a0<\/span>Moskalev<\/span>, “Realization of Partially Defined Logical Functions by Expansion into Orthogonal Series<\/a>,”\u00a0<\/span>Automata.\u00a0<\/span>and<\/span>\u00a0<\/span>Remote Control<\/em>, Vol. 31, No. 8, August 1970, pp. 1278-1288.<\/p>\n

      42. M. G. Karpovsky, I.L.\u00a0<\/span>Erosh<\/span>, “Error Correction in Arithmetical Devices Constructed by Multivalued Logical Cells<\/a>,”\u00a0<\/span>Theoretical Cybernetics<\/em>, No. 2, 1970 (Russian).<\/p>\n

      43. M. G. Karpovsky, E.S.\u00a0<\/span>Moskalev<\/span>, “Utilization of Autocorrelation Functions for Realization of Systems of Logical Functions<\/a>,”\u00a0<\/span>Automata.\u00a0<\/span>and<\/span>\u00a0<\/span>Remote Control<\/em>, Vol. 31, No. 2, February 1970, pp. 243-250.<\/p>\n

      44. M. G. Karpovsky, E.S.\u00a0<\/span>Moskalev<\/span>, “Tests for Non-Orientated Graphs<\/a>,”\u00a0<\/span>Automata.\u00a0<\/span>and<\/span>\u00a0<\/span>Remote Control<\/em>, Vol. 31, No. 4, April 1970, pp. 656-665.<\/p>\n

      45. M. G. Karpovsky, A.A.\u00a0<\/span>Troianovsky<\/span>, I.I.\u00a0<\/span>Sisoev<\/span>, “Investigation of a Biological System as an Automation with Error Correction<\/a>,”\u00a0<\/span>Automata. Control and Computer Science<\/em>, No. 6, 1971, pp. 77-81 (Russian).<\/p>\n

      46. M. G. Karpovsky,\u00a0<\/span>Yu.G<\/span>. Karpov, “Optimal Code Redundancy Methods for Error Correction in Finite Automata<\/a>,”\u00a0<\/span>Cybernetics<\/em>, July 1973, pp. 82-89.<\/p>\n

      47. M. G. Karpovsky, “Error Correction in Automata with Combinatorial Parts Realized by Expansion in Orthogonal Series<\/a>,”\u00a0<\/span>Automata.\u00a0<\/span>and<\/span>\u00a0<\/span>Remote Control<\/em>, Vol. 32, No. 93, Part 2, September 1971, pp. 1534-1528.<\/p>\n

      48. M. G. Karpovsky, E.S.\u00a0<\/span>Moskalev<\/span>, A.A.\u00a0<\/span>Troianovsky<\/span>, “Methods of Estimating of the Correcting Capability of Functions of Algebra of Logic<\/a>,”\u00a0<\/span>Izvestia<\/em><\/span>\u00a0<\/span>Acad.\u00a0<\/span>Nauk<\/span>\u00a0<\/span>USSR<\/em>, Vol. 12, No. 1, 1974, pp. 124-130.<\/p>\n

      49. M. G. Karpovsky, N.S.\u00a0<\/span>Tcherbakov<\/span>, “Automata with Transition Self-Correction<\/a>,”\u00a0<\/span>Cybernetics<\/em>, February 1971, pp. 63-66 (Russian).<\/p>\n

      50. M. G. Karpovsky,\u00a0<\/span>Yu.G<\/span>. Karpov, “Decomposition of Algebras and Synthesis of Reliable Discrete Devices by Integral Modules<\/a>,”\u00a0<\/span>Cybernetics<\/em>, Vol. 9, No. 3, February 1975 (Russian).<\/p>\n

      51. M. G. Karpovsky, A.A.\u00a0<\/span>Troianovsky<\/span>, “Methods for Analyzing the Correcting Power of Automata<\/a>,”\u00a0<\/span>Automatic Control and Computer Science<\/em>, Vol. 8, No. 1, 1974, pp. 22-27.<\/p>\n

      52. M. G. Karpovsky, “Harmonic Analysis over Finite Commutative Groups in Linearization Problems for Systems of Logical Functions<\/a>,”\u00a0<\/span>Information and Control<\/em>, Vol. 33, 1977, pp. 142-165.<\/p>\n

      53. M. G. Karpovsky, “Error Detection in Digital Devices and Computer Programs with the Aid of Linear Recurrent Equations over Finite\u00a0<\/span>Communative<\/span>\u00a0<\/span>Groups<\/a>,”\u00a0<\/span>IEEE Trans. on Computers<\/em>, C-26, No. 3, 1977, pp. 208-219.<\/p>\n

      54. M. G. Karpovsky, E.A. Trachtenberg, “Some Optimization Problems for Convolution Systems over Finite Groups<\/a>,”\u00a0<\/span>Information and Control<\/em>, Vol. 34, 1977, pp. 1-22.<\/p>\n

      55. M. G. Karpovsky, “Fast Fourier Transforms over a Finite Non-Abelian Group<\/a>,”\u00a0<\/span>IEEE Trans. on Computers<\/em>, C-26, No. 10, 1977, pp. 1028-1031.<\/p>\n

      56. M. G. Karpovsky, E.A. Trachtenberg, “Linear Checking Equations and Error-Correcting Capability for Computation Channels<\/a>,”\u00a0<\/span>Proc. IFIP Congress 1977<\/em>, North Holland, 1977, pp. 619-624.<\/p>\n

      57. M. G. Karpovsky, E.A. Trachtenberg, “Fourier Transforms Over Finite Groups for Error Detection and Error Correction in Computational Channels<\/a>,”\u00a0<\/span>Information and Control<\/em>, Vol. 40, No. 2, 1979, pp. 335-359.<\/p>\n

      58. M. G. Karpovsky, V.D.\u00a0<\/span>Milman<\/span>, “Coordinate Density of Subsets of Finite Homogeneous Spaces<\/a>,”\u00a0<\/span>Discrete Mathematics<\/em>, No. 22, 1978, pp. 273-281.<\/p>\n

      59. M. G. Karpovsky, “On Weight Distribution for Binary Linear Codes<\/a>,”\u00a0<\/span>IEEE Trans. on Inf. Theory<\/em>, IT-25, January, 1979, pp. 105-109.<\/p>\n

      60. M. G. Karpovsky, V.D.\u00a0<\/span>Milman<\/span>, “Coordinate Density of Sets of Vectors<\/a>,”\u00a0<\/span>Discrete Mathematics<\/em>, No. 24, 1978, pp. 171-184.<\/p>\n

      61. M. G.\u00a0<\/span>Karpovksy<\/span>, “Error Detection for Polynomial Computations<\/a>,”\u00a0<\/span>IEE Journal on Computer and Digital Techniques<\/em>, C-26, No. 6, June 1980, pp. 523-528.<\/p>\n

      62. M. G. Karpovsky, “Detection and Location of Input and Feedback Bridging Faults<\/a>,”\u00a0<\/span>IEEE Trans. on Computers<\/em>, C-26, No. 6, June 1980, pp. 523-528.<\/p>\n

      63. M. G. Karpovsky, “Weight Distribution of Translates, Covering Radius and Perfect Codes Correcting Errors of the Given Weights<\/a>,”\u00a0<\/span>IEEE Trans. Info. Theory<\/em>, July 1981, pp. 462-472.<\/p>\n

      64. M. G. Karpovsky, “Testing for Numerical Computations<\/a>,”\u00a0<\/span>IEEE Proc.<\/em>, Vol. 127, pt. E, No. 2, March 1980, pp. 69-77.<\/p>\n

      65. M. G. Karpovsky, “An Approach for Error Detection and Error Correction in Distributed Systems Computing Numerical Functions<\/a>,”\u00a0<\/span>IEEE Trans. on Computers<\/em>, No. 12, December 1981, pp. 947-954.<\/p>\n

      66. M. G. Karpovsky, S. Su, “Detection of Bridging and Stuck-At Faults at Input and Output Pins of Standard Computer Components<\/a>,”\u00a0<\/span>Proc. of 17th Design Automation Conference<\/em>, 1980, pp. 494-506.<\/p>\n

      67. M. G. Karpovsky, “Spectral Methods for Decomposition, Design and Testing of Multiple-Valued Logical Networks<\/a>,” Keynote Paper,\u00a0<\/span>Proc. of International Symposium on Multiple-Valued Logic<\/em>, Oklahoma, 1981, pp. 1-10.<\/p>\n

      68. M.\u00a0<\/span>Deza<\/span>, M. G. Karpovsky, V.S.\u00a0<\/span>Milman<\/span>, “Codes Correcting and Arbitrary Sets of Errors<\/a>,”\u00a0<\/span>Revue de\u00a0<\/span>Cethedec<\/span><\/em>, No. 66, 1981 (French).<\/p>\n

      69. M. G. Karpovsky, “Detection and Location of Error by Linear Inequality Checks<\/a>,”\u00a0<\/span>Proc. IEE<\/em>, Vol. 129, No. 3, May 1982, pp. 86-92.<\/p>\n

      70. N.\u00a0<\/span>Goel<\/span>, M. G. Karpovsky, “Functional Testing of Computer Hardware Based on Minimization of Magnitude of Undetected Errors<\/a>,”\u00a0<\/span>IEE Journal on Computer and Digital Techniques<\/em>, Vol. 129, No. 5, September 1982, pp. 169-181.<\/p>\n

      71. M. G. Karpovsky, “Testing for Multiple Valued Computations<\/a>,”\u00a0<\/span>Proc. 12th International Symposium on Multiple Valued Logic<\/em>, Paris, France, 1982.<\/p>\n

      72. M. G. Karpovsky, “Universal Tests Detecting\u00a0<\/span>Input\/Output<\/span>\u00a0<\/span>Faults in Almost All Devices<\/a>,”\u00a0<\/span>Proc. of 1982 International Test Conference<\/em>, Cherry Hill, NJ, 1982, pp. 52-57.<\/p>\n

      73. M. G. Karpovsky, “Universal Tests for Detection of\u00a0<\/span>Input\/Output<\/span>\u00a0<\/span>Stuck-At and Bridging Faults<\/a>,”\u00a0<\/span>IEEE Trans. on Computers<\/em>, Vol. C-32, December 1983, pp. 1194-1198.<\/p>\n

      74. K. K.\u00a0<\/span>Saluja<\/span>, M. G. Karpovsky, “Testing Computer Hardware through Data Compression in Space and Time<\/a>,”\u00a0<\/span>Proc. of 1983 International Test Conference<\/em>, Cherry Hill, NJ, 1983, pp. 83-89.<\/p>\n

      75. M. G. Karpovsky, L.B. Levitin, “Detection and Identification of\u00a0<\/span>Input\/Output<\/span>\u00a0<\/span>Stuck-At and Bridging Faults in Combinational and Sequential VLSI Networks by Universal Tests<\/a>,”\u00a0<\/span>Integration the VLSI Journal<\/em>, November 1983, pp. 22-24.<\/p>\n

      76. M. G. Karpovsky, “Memory Testing by Linear Checks<\/a>,”\u00a0<\/span>IEEE Journal on Computer and Digital Techniques<\/em>, Vol. 131, pt. E, No. 5, September 1984, pp. 158-168.<\/p>\n

      77. M. G. Karpovsky, R.G. Van Meter, “An Approach to the Testing of Microprocessors<\/a>,” Proc. 1984,\u00a0<\/span>Design Automation Conference<\/em>, Albuquerque, New Mexico, 1984, pp. 196-202.<\/p>\n

      78. G. Cohen, M. G. Karpovsky, H.F. Mattson Jr., J.R.\u00a0<\/span>Shatz<\/span>, “Covering Radius Survey and Recent Results<\/a>,”\u00a0<\/span>IEEE Trans. on Information Theory<\/em>, May 1985, Vol. IT-31, pp. 328-344.<\/p>\n

      79. M. G. Karpovsky, E.A. Trachtenberg, “Statistical and Computational Performance of a Class of Generalized Wiener Filters<\/a>,”\u00a0<\/span>IEEE Trans. on Information Theory<\/em>, May 1986, pp. 303-307.<\/p>\n

      80. G. Cohen, P.\u00a0<\/span>Godlewski<\/span>, M.G. Karpovsky, “Exhaustive Tests for Combinational Networks<\/a>,”\u00a0<\/span>Journal\u00a0<\/span>Fransais<\/span>\u00a0<\/span>de\u00a0<\/span>Theorie<\/span>\u00a0<\/span>du Signal<\/em>, Vol. 2, No. 2, 1984, pp. 223-226.<\/p>\n

      81. S. M. Reddy, K.K.\u00a0<\/span>Saluja<\/span>, M.G. Karpovsky, “A Data Compression Technique for Built-In\u00a0<\/span>Self Test<\/span><\/a>,”\u00a0<\/span>Proc. of 1985 Fault-Tolerant Computing Symposium<\/em>, 1985, pp. 294-299.<\/p>\n

      82. M. G. Karpovsky, E.A.\u00a0<\/span>Moskalev<\/span>, “Covering of Edges of Graph by a Minimal Set of Paths,”\u00a0<\/span>Discrete Mathematics<\/em>, Vol. 58, No. 2, February 1986.<\/p>\n

      83. M. G. Karpovsky, “Multilevel Logical Networks<\/a>,”\u00a0<\/span>IEEE Trans. on Computers<\/em>, C-36, No. 2, 1987, pp. 215-225.R<\/p>\n

      84. S. R. Reddy, K. K.\u00a0<\/span>Saluja<\/span>, M. G. Karpovsky, “Data Compression Techniques for Test responses<\/a>,”\u00a0<\/span>IEEE Trans. on Computers<\/em>, September 1988, pp. 1151-1156.<\/p>\n

      85. M. G. Karpovsky, “Recent Developments in Applications of Spectral Techniques in Logic Design and Testing of Computer Hardware<\/a>,” Keynote Paper,\u00a0<\/span>Proc. of Second International Symposium on Spectral Techniques<\/em>, Montreal, Canada, 1986, pp. 1-10.<\/p>\n

      86. T.\u00a0<\/span>Damarla<\/span>, M. G. Karpovsky, “Reed-Muller Transforms for Fault Detection<\/a>,”\u00a0<\/span>Proc. Second International Workshop on Spectral Techniques<\/em>, Montreal, Canada, October 1986.<\/p>\n

      87. T.\u00a0<\/span>Damarla<\/span>, M. G. Karpovsky, “Fault Detection in Combinational Networks by Reed-Muller Transforms<\/a>,”\u00a0<\/span>IEEE Trans. on Computers<\/em>, Vol. 38, June 1989, pp. 788-798.<\/p>\n

      88. M. G. Karpovsky, P.\u00a0<\/span>Nagvajara<\/span>, “Optimal Time and Space Compression of Test Responses for VLSI Devices<\/a>,”\u00a0<\/span>Proc. The International Test Conference<\/em>, 1987, pp. 523-529.<\/p>\n

      89. E. A. Trachtenberg, A. H.\u00a0<\/span>Chaudhri<\/span>, M. G. Karpovsky, “Blackout Detection as a\u00a0<\/span>Multiobjective<\/span>\u00a0<\/span>Optimization Problem,”\u00a0<\/span>Proc. of 1987 International Symposium of Test and Evaluation\u00a0<\/span>Assocs.,<\/span><\/em>\u00a0<\/span>Boston, 1987.<\/p>\n

      90. T. Roziner, M. G. Karpovsky, E. A. Trachtenberg, “Fast Fourier Transforms over Finite Groups on Multiprocessor Systems<\/a>,”\u00a0<\/span>IEEE Trans. on Acoustics, Speech, and Signal Processing<\/em>, February 1990.<\/p>\n

      91. T. Roziner, M. G. Karpovsky, E. A. Trachtenberg, “Complexity Analysis for Generalized Fast Fourier Transforms in Multiprocessor Environment<\/a>,”\u00a0<\/span>Proc. 12th IMAC World Congress<\/em>, Paris, France, 1988.<\/p>\n

      92. M. G. Karpovsky, P.\u00a0<\/span>Nagvajara<\/span>, “Optimal Robust Compression of Test Responses<\/a>,”\u00a0<\/span>IEEE Trans. on Computers<\/em>, Vol. 39, No. 1, pp. 138-141, January 1990.<\/p>\n

      93. E. A. Trachtenberg, M. G. Karpovsky, “Optimal Varying Dyadic Structure Models of Time Invariant Systems<\/a>,”\u00a0<\/span>Proc. 1988 IEEE Symposium on Circuits and Systems<\/em>, Helsinki, 1988, pp. 1111-1115.<\/p>\n

      94. M. G. Karpovsky, P.\u00a0<\/span>Nagvajara<\/span>, “Optimal Codes for the\u00a0<\/span>Minimax<\/span>\u00a0<\/span>Criterion on Error Detection<\/a>,”\u00a0<\/span>IEEE Trans. on Information Theory<\/em>, November 1989.<\/p>\n

      95. M. G. Karpovsky, P.\u00a0<\/span>Nagvajara<\/span>, “Board Level Diagnosis by Signature Analysis<\/a>,”\u00a0<\/span>Proc. International Test Conference<\/em>, 1988, pp. 47-53.<\/p>\n

      96. M. G. Karpovsky, P.\u00a0<\/span>Nagvajara<\/span>,\u00a0<\/span>”\u00a0<\/span>Functions with Flat Autocorrelation and Their Generalizations<\/a>,”\u00a0<\/span>Proc. 3rd International Workshop on Spectral Techniques<\/em>, W. Germany, 1988.<\/p>\n

      97. P.\u00a0<\/span>Nagvajara<\/span>, M. G. Karpovsky, “Signature Analysis by Quadratic Compressors<\/a>,”\u00a0<\/span>Proc. Test and Instrumentation Conference<\/em>, Boston, 1988, pp. 751-758.<\/p>\n

      98. M. G. Karpovsky, P.\u00a0<\/span>Nagvajara<\/span>, “Design of Self-Diagnostic Boards by Signature Analysis<\/a>,”\u00a0<\/span>IEEE Trans. on Industrial Electronics<\/em>, May 1989, pp 241-246.<\/p>\n

      99. T.\u00a0<\/span>Damarla<\/span>, M. G. Karpovsky, “Detection of Stuck-At and Bridging Faults in Reed-Muller Canonical Networks<\/a>,”\u00a0<\/span>IEEE Proc.<\/em>, Vol. 136, No. 5, pp. 430-433, 1989.<\/p>\n

      100. M. G. Karpovsky, E. A. Trachtenberg, T. Roziner, “Computation of Discrete Fourier Transforms over Finite Abelian Groups Using Pipelined and Systolic Array Architectures<\/a>,”\u00a0<\/span>Proc. of International Symposium on the Mathematical Theory of Networks and Systems<\/em>, Amsterdam, Netherlands, 1989.<\/p>\n

      101. D. K. Pradhan, S. K. Gupta, M. G. Karpovsky, “Aliasing Probability for Multiple Input Signature Analyzer<\/a>,”\u00a0<\/span>IEEE Trans. on Computer<\/em>, April 1990.<\/p>\n

      102. T.\u00a0<\/span>Damarla<\/span>, M. G. Karpovsky, “Multiple Fault Detection in a Network of Functions<\/a>,”\u00a0<\/span>IETE Journal<\/em>, Vol. 35, No. 6, 1989.<\/p>\n

      103. M. G. Karpovsky, L. B. Levitin, F. S.\u00a0<\/span>Vainstein<\/span>, “Identification of Faulty Processing Elements by Space-Time Compression of Test Responses<\/a>,”\u00a0<\/span>Proc. International Test Conference<\/em>, 1990, pp. 638-647.<\/p>\n

      104. P.\u00a0<\/span>Nagvajara<\/span>, M. G. Karpovsky, L. B. Levitin, “Pseudorandom Test Patterns Generation for Boundary Scan Design<\/a>,”\u00a0<\/span>IEEE Journal on Design and Test of Computers<\/em>, September 1991, pp. 58-65.<\/p>\n

      105. T. Roziner, M. G. Karpovsky, “Multidimensional Fourier Transforms by Systolic Architectures<\/a>,”\u00a0<\/span>Journal of VLSI Signal Processing<\/em>, No. 4, 1992, pp. 343-354.<\/p>\n

      106. M. G. Karpovsky, D. K. Pradhan, S. K. Gupta, “Aliasing and Diagnostic Probabilities in MISR and STUMPS Using a General Error Model<\/a>,”\u00a0<\/span>Proc. International Test Conference<\/em>, 1991, pp. 828-840.<\/p>\n

      107. P.\u00a0<\/span>Nagvajara<\/span>, M. G. Karpovsky, L. B. Levitin, “Efficient Test Generation for Built-In Self-Test Boundary-Scan Template<\/a>,”\u00a0<\/span>9th Annual IEEE VLSI Test Symposium<\/em>, Atlantic City, NJ, 1991, pp. 277-284.<\/p>\n

      108. P.\u00a0<\/span>Nagvajara<\/span>, M. G. Karpovsky, “Built-In Self-Diagnostic Read-Only-Memories<\/a>,”\u00a0<\/span>Proc. International Test Conference<\/em>, 1991, pp. 695-704.<\/p>\n

      109. P.\u00a0<\/span>Nagvajara<\/span>, M. G. Karpovsky, “Coset Error Detection in BIST Design<\/a><\/span>,”\u00a0<\/span>IEEE VLSI Test Symposium<\/em>, Atlantic City, NJ, 1992, pp. 79-84.<\/p>\n

      110. M. G. Karpovsky, L. B. Levitin, F. S.\u00a0<\/span>Vainstein<\/span>, “Diagnosis by Signature Analysis of Test Responses<\/a>,”\u00a0<\/span>IEEE Trans. on Computers<\/em>, Vol. 43, No. 2,\u00a0<\/span>Februrary<\/span>\u00a0<\/span>1994, pp. 141-153.<\/p>\n

      111. M. G. Karpovsky, S. Chaudhry, “Built-In Self-Diagnostic by Space-Time Compression of Test Responses,”\u00a0<\/span>IEEE VLSI Test Symposium<\/em>, Atlantic City, NJ, 1992, pp. 149-155.<\/p>\n

      112. M. G. Karpovsky, S. Chaudhry, “Design of Self-Diagnostic Boards by Multiple Signature Analysis<\/a>,”\u00a0<\/span>IEEE Trans. on Computers<\/em>, Vol. 42, No. 9, September 1993, pp. 1035-1044.<\/p>\n

      113. M. G. Karpovsky, S. Chaudhry, L. B. Levitin, “Multiple Signature Analysis: a Framework for Built-In Self-Diagnostic<\/a>,”\u00a0<\/span>Fault-Tolerant Computing Symposium<\/em>, Boston, 1992, pp. 112-120.<\/p>\n

      114. M. G. Karpovsky, T. Roziner, C. Moraga, “Error Detection in Multiprocessor Systems and Array Processors<\/a>,”\u00a0<\/span>IEEE Trans. on Computers<\/em>, Vol. 44, No. 3, March 1995, pp. 383-394.<\/p>\n

      115. M. G. Karpovsky, S. Chaudhry, L. B. Levitin, C. Moraga, “Detection and Location of Given Sets of Errors by\u00a0<\/span>Nonbinary<\/span>\u00a0<\/span>Linear Codes<\/a>,” Springer and\u00a0<\/span>Verlag<\/span>,\u00a0<\/span>Lecture Notes<\/em>, No. 781, 1994, pp. 172-194.<\/p>\n

      116. M. G. Karpovsky, V. N.\u00a0<\/span>Yarmolik<\/span>, “Transparent Memory BIST<\/a>,”\u00a0<\/span>Proc. International Workshop on Memory Technology<\/em>, 1994, pp. 106-112.<\/p>\n

      117. M. G. Karpovsky, “Spectral Techniques for Off-Line Testing and Diagnosis of Computer Systems<\/a>,” Keynote paper,\u00a0<\/span>Proc. of Fifth International Symposium on Spectral Techniques<\/em>, China, 1994, pp. 172-194.<\/p>\n

      118. M. G. Karpovsky, V. N.\u00a0<\/span>Yarmolik<\/span>, “Transparent Memory Testing for Pattern Sensitive Faults<\/a>,”\u00a0<\/span>Proc. International Test Conference<\/em>, 1994, pp. 860-870.<\/p>\n

      119. E. P.\u00a0<\/span>Kalosha<\/span>, V. N.\u00a0<\/span>Yarmolik<\/span>, M. G. Karpovsky, “Signature Testability of PLA<\/a>,”\u00a0<\/span>Fourth International Workshop on Field Programmable Logic<\/em>, 1994, pp. 126-132.<\/p>\n

      120. M. G. Karpovsky, V. N.\u00a0<\/span>Yarmolik<\/span>, A. J. van de\u00a0<\/span>Goor<\/span>, “Pseudoexhaustive Word-Oriented DRAM Testing<\/a><\/span>,”\u00a0<\/span>Proc. 1995 European Design and Test Conference<\/em>, 1995, pp. 126-132.<\/p>\n

      121. M. G. Karpovsky, “Application of Spectral Techniques for Off-Line Testing and Fault-Tolerant Computing,”\u00a0<\/span>Berichte<\/em><\/span>\u00a0<\/span>zur<\/span>\u00a0<\/span>Angewandten<\/span>\u00a0<\/span>Informatik<\/span><\/em>, 1995.<\/p>\n

      122. L. B. Levitin, M. G. Karpovsky, “Exhaustive Testing of Almost All Devices…<\/a>,”\u00a0<\/span>Open Systems and Information Dynamics<\/em>, Vol. 2, No. 3, 1994, pp. 1-16.<\/p>\n

      123. M. G. Karpovsky, V. N.\u00a0<\/span>Yarmolik<\/span>, “Testability Measures and Test Complexities for Testing with Internal Access<\/a>,”\u00a0<\/span>Proc. Int. Workshop on IDDQ Testing<\/em>, pp. 9-14, 1995.<\/p>\n

      124. V. N.\u00a0<\/span>Yarmolik<\/span>, Y. V.\u00a0<\/span>Bykov<\/span>, M. G. Karpovsky, “Test Sets for Internal Access Testing<\/a>,”\u00a0<\/span>Proc. Int. Conference on Computer-Aided Design<\/em>, pp. 135-141, 1995.<\/p>\n

      125. M. G. Karpovsky, D. Das, H.\u00a0<\/span>Varhan<\/span>, “Built-In Self-Testing for Detection of Coupling Faults in Semiconductor Memories<\/a>,”\u00a0<\/span>Proc. Int. IEEE Workshop on Memory Technology, Design and Testing<\/em>, 1996.<\/p>\n

      126. M. G. Karpovsky, V. N.\u00a0<\/span>Yarmolik<\/span>, “Transparent Random Access Memory Testing…<\/a>,”\u00a0<\/span>Journal of Electronic Testing: Theory and Applications<\/em>, Vol. 9, No. 3, 1996, pp. 261-266.<\/p>\n

      127. V. N.\u00a0<\/span>Yarmolik<\/span>, A. I.\u00a0<\/span>Yanushkevich<\/span>, M. G. Karpovsky, “IDDQ Testing of Systolic CMOS Networks,”\u00a0<\/span>Microelectronics, Bulletin Russian Academy of Science<\/em>, Vol. 26, No. 1, 1997, pp. 25-29.<\/p>\n

      128. D. Das, M. G. Karpovsky, “Exhaustive and Near Exhaustive Memory Testing and their BIST Implementations<\/a>,”\u00a0<\/span>Journal of Electronic Testing: Theory and Applications<\/em>, Vol. 10, No. 3, June 1997, pp. 215-229.<\/p>\n

      129. C. Moraga, R.\u00a0<\/span>Oenning<\/span>, M. G. Karpovsky, “Zhang\u00a0<\/span>Watari<\/span>\u00a0<\/span>Transform..<\/a>.,”\u00a0<\/span>Multivalued Logic<\/em>, Vol. 2, 1997, pp. 245-262.<\/p>\n

      130. M. G. Karpovsky, “Integrated On-Line and Off-Line Error Detection Mechanism in the Coding Theory Framework<\/a>,”\u00a0<\/span>VLSI Design<\/em>, Vol. 5, No. 4, 1998, pp. 313-331.<\/p>\n

      131. K.\u00a0<\/span>Chakrabarty<\/span>, M. G. Karpovsky, L. B. Levitin, “Fault Isolation and Diagnosis in Multiprocessor Systems with Point-to-Point Connections<\/a>,” in\u00a0<\/span>Fault Tolerant Parallel and Distributed Systems<\/em>, Kluwer Academic Publishers, 1998, pp. 285-301.<\/p>\n

      132. M. G. Karpovsky, K.\u00a0<\/span>Chakrabarty<\/span>, L. B. Levitin, “A New Class of Codes for Identification of Vertices in Graphs<\/a>,”\u00a0<\/span>IEEE Trans. Info Theory<\/em>, March 1998, Vol. 46, pp. 599-611.<\/p>\n

      133. L.\u00a0<\/span>Zakrevsky<\/span>, M. G. Karpovsky, “Fault Tolerant Message Routing For Multiprocessors<\/a>,” in\u00a0<\/span>Parallel and Distributed Processing (J.\u00a0<\/span>Rolim<\/span>\u00a0<\/span>Editor)<\/em>, Springer, 1998, pp. 714-731.<\/p>\n

      134. I. Levin, M. G. Karpovsky, “On-Line Self-Checking of\u00a0<\/span>Microprogram<\/span>\u00a0<\/span>Control Units<\/a>,”\u00a0<\/span>Proc. 4th Int. Workshop on On-Line Testing<\/em>, 1998, pp. 152-157.<\/p>\n

      135. M. G. Karpovsky, “Spectral Techniques for Off-Line Testing and Diagnosis of <\/a>Computer Systems<\/a>,”\u00a0<\/span>Approximation Theory and Its Applications<\/em>, 1998, pp. 55-72.<\/p>\n

      136.\u00a0<\/span>L.Zakrevski<\/span>, M.G. Karpovsky,\u00a0<\/span>S.Yang<\/span>, \u201d<\/span>BIST for Embedded Drams<\/a>\u201d,\u00a0<\/span>Proc. Int. Workshop<\/em>\u00a0<\/span>on Memory Technology<\/em>, 1998.<\/p>\n

        \n
      1. <\/span>M.G.Karpovsky<\/span>,<\/span>K.Chakrabarty<\/span>,\u00a0<\/span>L.B.Levitin<\/span>,\u00a0<\/span>D.Avresky<\/span>, \u201cOn\u00a0<\/span>the\u00a0\u00a0Covering<\/span>\u00a0<\/span>of Vertices for Fault-Diagnosis in\u00a0<\/span>Hypercubes<\/span><\/a>\u201d,\u00a0<\/span>Information Processing Letters<\/em>, 69, 1999, pp.99-103.<\/li>\n
      2. <\/span>L.Zakrevski<\/span>,<\/span>M.G.Karpovsky<\/span>, \u201cFault-Tolerant Routing in Computer Networks<\/a>\u201d,\u00a0<\/span>Proc. Int.<\/em>\u00a0<\/span>Conf. On Parallel and Distributed Processing Techniques and Applications<\/em>, vol.4, 1999, pp.2279-2287.<\/li>\n
      3. <\/span>L.Zakrevski<\/span>,<\/span>S.Jaiswal<\/span>,\u00a0<\/span>L.B.Levitin<\/span>,\u00a0<\/span>M.G.Karpovsky<\/span>, \u201d<\/span>A New Method for Deadlock Elimination in Computer Networks with Irregular Topologies<\/a>\u201d,\u00a0<\/span>Proc. Int. Conf. On Parallel and<\/em>\u00a0<\/span>Distributed Computer Systems<\/em>,vol.1<\/span>, pp396-402, 1999.<\/li>\n
      4. <\/span>L.Zakrevski,S.Jaiswal<\/span>,<\/span>M.G.Karpovsky<\/span>,\u00a0<\/span>“Unicast Message Routing in Communication Networks with Irregular Topologies<\/a>“<\/u>Proc. of CAD-99<\/em>, 1999.<\/li>\n<\/ol>\n

        141.S.Jaiswal<\/span>,\u00a0<\/span>M.Mustafa<\/span>,\u00a0<\/span>L.Zakrevski<\/span>,\u00a0<\/span>M.G.Karpovsky<\/span>, “Wormhole Message Routing in Networks of Workstations”,\u00a0<\/span><\/a>Proc.of<\/em><\/span>\u00a0<\/span><\/em>\u00a0\u00a0<\/span>PDCS-2000,\u00a0 pp.169-174<\/em><\/p>\n

          \n
        1. <\/span>L.Zakrevski<\/span>,<\/span>M.Mustafa<\/span>,\u00a0<\/span>M.G.Karpovsky<\/span>, “Turn Prohibition Based Routing in Irregular Computer Networks<\/a>“,\u00a0<\/span>Proc. of PDCS-2000, pp.174-179<\/em><\/li>\n
        2. <\/span>M.G.Karpovsky,I.Levin<\/span>,<\/span>V.Sinelnikov<\/span>,\u00a0<\/span>R.Goot<\/span>, “New Architecture for Sequential Machines with Self-Error-Detection<\/a>“,\u00a0<\/span>Proc.\u00a0<\/span>Int.Conf.on<\/span>\u00a0<\/span>New<\/em>\u00a0<\/span>Information Technologies<\/em>,\u00a0<\/span>NITe’s<\/span>\u00a0<\/span>2000, pp.111-117<\/li>\n
        3. <\/span>M.G.Karpovsky,R.S.Stankovic<\/span>,<\/span>C.Moraga<\/span>, “Spectral Techniques in Binary and Multiple-Valued Switching Theory<\/a>“\u00a0<\/span>Proc.<\/em>\u00a0<\/span>Int.Symp.on<\/em><\/span>\u00a0<\/span>Multivalued Logic<\/em>, May 2001, pp41-46<\/li>\n
        4. <\/span>U.Blass<\/span>,<\/span>I.Honkala<\/span>,\u00a0<\/span>M.G.Karpovsky<\/span>, S.\u00a0<\/span>Litsyn<\/span>, “Short Dominating Paths and Cycles in\u00a0<\/span>Hypercubes<\/span><\/a>“,\u00a0<\/span>Annals of Combinatorics 5<\/em>, 2001, pp. 51-59.<\/li>\n
        5. <\/span>M.G.Karpovsky<\/span>,<\/span>R.S.Stankovic<\/span>,\u00a0<\/span>J.T.Astola<\/span>, “Spectral Techniques for Design and Testing of Computer Hardware<\/a>“,\u00a0<\/span>Keynote Pape<\/em><\/strong>r, Proc. First Int. Workshop on\u00a0Spectral Techniques and Logical Design for Future<\/em>\u00a0<\/span>Digital Systems<\/em>, Tampere, Finland, June, 2000, pp.9-43.<\/li>\n
        6. <\/span>P.K.Lala<\/span>,<\/span>M.G.Karpovsky<\/span>, “An Approach for Designing On-line Testable State Machines<\/a>“,\u00a0<\/span>Proc. International Workshop on On-line Testing<\/em>, 2001.<\/li>\n
        7. I. Levin, V.<\/span>Sinelnikov<\/span>, M. Karpovsky, “Synthesis of ASM-based Self-Checking Controllers”,<\/span><\/a>Proceedings of International Conference on Digital Systems Design<\/em>, DSD’2001.<\/li>\n
        8. I. Levin, M. Karpovsky, V.<\/span>Sinelnikov<\/span>, “Architecture of FPGA-based Concurrent Checking FSM”,<\/span><\/a>Proceedings of the Third International Electronic Circuits and Systems Conference,\u00a0<\/span><\/em>Bratislava, Slovakia, September 5-7, 2000.<\/li>\n
        9. M. Karpovsky, R. Stankovic, J. Astola, “Construction of Linearly Transformed Binary Decision Diagrams by Autocorrelation Functions<\/a>“,<\/span>Proceedings of International TICSP Workshop on Spectral Methods and<\/span>Multirate<\/span>\u00a0<\/span>Signal Processing, SMMSP’2001<\/em>, Pula, Croatia, 2001.<\/li>\n
        10. M. Karpovsky, L.<\/span>Zakrevski<\/span>, M. Mustafa, A. Agarwal, “The Generalized Turn Prohibition Model for Multicast Routing in Irregular Networks<\/a>,”<\/span>Proc. of Thirteenth IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS 2001)<\/em>,Anaheim, California, USA, August 21-24, 2001.<\/li>\n
        11. A. Trachtenberg, M. Karpovsky, “Space-Time Turn Prohibitions for Low Density Parity-Check Codes<\/a>“,<\/span>Proc. of 39th Annual Allerton Conference on Communication, Control<\/em>,<\/span>and Computing<\/em>, 2001.<\/li>\n
        12. M. Karpovsky, L. Levitin, A. Trachtenberg, “Data Verification and Reconciliation with Generalized Error Control Codes<\/a>“,<\/span>Proc. of 39th Annual Allerton Conference on Communication, Control, and Computing<\/em>, 2001.<\/li>\n
        13. D. Starobinski,<\/span>M.G.Karpovsky<\/span>, L.<\/span>Zakrevski<\/span>, “Application of Network Calculus to General Topologies Using Turn Prohibitions”<\/a>,\u00a0<\/span>Proc. INFOCOM<\/em>\u00a0<\/span>2002.<\/li>\n
        14. <\/strong><\/span>M. Karpovsky, R. Stankovic,<\/span>C.Moraga<\/span>,\u00a0<\/span>“Spectral Techniques in Binary and Multiple-Valued Switching Theory<\/a>“,\u00a0<\/span>International Journal on Multiple-Valued Logic,\u00a0<\/span><\/em>Vol. 10, No3, 2004.<\/li>\n
        15. <\/span>D.Starobinski<\/span>,<\/span>M.G.Karpovsky<\/span>,\u00a0<\/span>L.Zakrevsky<\/span>\u00a0<\/span>“Applications of Network Calculus to General Topologies<\/a>“\u00a0\u00a0IEEE<\/em><\/span>\/ACM Transactions on Networking<\/em>, June 2003, vol. 11, No.\u00a03, pp 411-422<\/li>\n
        16. <\/span>I.Honkala<\/span>,<\/span>M.G.Karpovsky<\/span>,\u00a0<\/span>S.Litsyn<\/span>\u00a0<\/span>“Cycles Identifying Vertices and Edges in Binary\u00a0<\/span>Hypercubes<\/span>\u00a0<\/span>and Two-Dimensional Tori”<\/a>,\u00a0\u00a0Discrete<\/em><\/span>\u00a0<\/span>Applied Mathematics<\/em>, vol129, No 2-3, 2003, pp.409-418<\/li>\n
        17. <\/span>I.Levin<\/span>, M. G. Karpovsky, S.<\/span>Ostanin<\/span>, “Sequential Circuits applicable for Detection of Faults”<\/a>,\u00a0<\/span>Proc. of 8th\u00a0<\/span>Int.Workshop<\/span>\u00a0<\/span>on On-Line Testing, 2002.<\/em><\/li>\n
        18. <\/span>I.Honkala<\/span>,<\/span>M.G.Karpovsky<\/span>,\u00a0<\/span>S.Litsyn<\/span>, “On Identification of Vertices and Edges Using Cycles”,\u00a0<\/span>Proc. AAECC-14, 2001, pp. 308-314<\/em><\/li>\n
        19. <\/span>M.G.Karpovsky<\/span>,<\/span>R.Stankovic<\/span>,\u00a0<\/span>C.Moraga<\/span>,\u00a0<\/span>“Recent Results in Applications of Spectral Techniques in Binary and Multiple-Valued Switching Theory”<\/a>,\u00a0<\/span>Proc<\/span>\u00a0<\/span>of Int.\u00a0<\/span>Conf<\/span>\u00a0<\/span>on Computer Intelligence and Information Technologies, pp.51-57, 2001<\/em><\/li>\n
        20. <\/span>M.G.Karpovsky<\/span>,<\/span>R.Stancovic<\/span>, J.\u00a0<\/span>Aastola<\/span>, “Reduction of Sizes of Decision Diagrams by Autocorrelation\u00a0<\/span>Fuctions<\/span><\/a>“,\u00a0<\/span>IEEE Trans on Computers, May, 2003, pp.592-607 \u00a0<\/em><\/li>\n
        21. I. Levin, V.<\/span>Ostrovsky<\/span>, S.<\/span>Ostanin<\/span>, M.G. Karpovsky,\u00a0<\/span>“Self-Checking Sequential Circuits with Self-Healing”<\/a>,\u00a0<\/span>Proc<\/em><\/span>\u00a0<\/span>of VLSI Symposium GLSVLSI-2002, 2002<\/em><\/li>\n
        22. 163<\/em>. R.<\/span>Stancovic<\/span>, M.G. Karpovsky, “Remarks on the Number of Logical Networks with the Same Complexity Derived from Spectral Decision Diagrams”,<\/span><\/a> Int. TICS Workshop on Spectral Methods and\u00a0<\/span>Multirate<\/span>\u00a0<\/span>Signal Processing, SMMSP’02, Toulouse, France, September 7-8, 2002, pp163-170.<\/em><\/em>164. L.B. Levitin, M.G. Karpovsky, “Deadlock Prevention in Networks Modeled as Weighted Graphs”,\u00a0<\/span>Proc. ICINSAT-2002\u00a0<\/span>Conf<\/span>, 2002, pp. 42-47.\u00a0<\/em><\/li>\n
        23. <\/span>M.G.Karpovsky<\/span>,<\/span>M.Mustafa<\/span>,\u00a0<\/span>R.Mathur<\/span>,\u00a0<\/span>“Fault-tolerant Unicast Wormhole Routing in Irregular Computer Networks”,<\/a>\u00a0<\/span>Proc. of the Conference on Parallel and Distributed Computing and Systems, PDCS 2002\u00a0<\/em><\/li>\n
        24. <\/span><\/em>A.Taubin<\/span>,<\/span>M.G.Karpovsky<\/span>, “Devices Resistant to Attacks. Design methodology”,<\/a>\u00a0<\/span>Proc<\/em><\/span>\u00a0<\/span>of IEEE\u00a0<\/span>Conf<\/span>\u00a0<\/span>on Technologies for Homeland Security, 2002<\/em><\/li>\n
        25. <\/span><\/em>M.G.Karpovsky<\/span>,<\/span>L.B.Levitin<\/span>,\u00a0<\/span>A.Trachtenberg<\/span>, “Data Verification and Reconciliation with Generalized Error Correcting Codes<\/a>“,\u00a0<\/span>IEEE Trans. on Information Theory<\/em>, Vol. 49, No.7, July 2003, pp.1788-1794.<\/li>\n
        26. De<\/span><\/span>Pelegrini<\/span>,\u00a0<\/span>D.Starobinski<\/span>,\u00a0<\/span>M.G.Karpovsky<\/span>,\u00a0<\/span>L.B.Levitin<\/span>, “Scalable Cycle Breaking Algorithms\u00a0<\/span>For<\/span>\u00a0<\/span>Gigabit Ethernet Backbones”<\/a>,\u00a0<\/span>Proc.\u00a0<\/span>Infocom<\/span>\u00a0<\/span>2004\u00a0<\/em><\/li>\n<\/ol>\n
            \n
          1. G.Karpovsky<\/span>,<\/span>R.Stancovic<\/span>\u00a0<\/span>and\u00a0<\/span>J.Aastola<\/span>, “Construction of Linearly Transformed Planar BDDs by Walsh Coefficients<\/a>“,\u00a0<\/span>Proc. ISCAS,<\/em>\u00a0<\/span>2004<\/li>\n
          2. <\/strong><\/span>M.G.Karpovsky\u00a0<\/span><\/span>and A. Taubin, “A New Class of Nonlinear Systematic Error Detecting Codes<\/a>“,\u00a0\u00a0IEEE<\/em><\/span>\u00a0<\/span>Trans Info Theory,\u00a0<\/span><\/em>Vol<\/span>\u00a0<\/span>50, No.8, 2004, pp.1818-1820<\/li>\n
          3. Kolotov<\/span><\/span>, Levin, I.,\u00a0<\/span>Ostrovsky<\/span>\u00a0<\/span>V., Karpovsky M.G, “Software Tool for BDD Optimizing by Using Autocorrelation Functions”.\u00a0<\/span>Proc. of the 23-th IEEE Convention of EEEI, 2004, pp129-132.<\/em><\/li>\n
          4. Levin<\/span>,<\/span>M.G.Karpovsky<\/span>,\u00a0<\/span>S.Ostanin<\/span>,\u00a0<\/span>V.Sinelnikov<\/span>, “Designing Circuits Detecting Different Types of Faults”,\u00a0<\/span>WSEN Transactions on Electronics, Issue 2, Vol. 1, Apr 2004, pp.396-404<\/em>. Karpovsky, M.G., K. Kulikowski, and A. Taubin, “Robust Protection Against Fault-Injection Attacks on Smart Cards Implementing the Advanced Encryption Standard”<\/a>,<\/span> Int. Conference on Dependable Systems and Networks (DNS 2004)<\/em>, July, 2004<\/li>\n
          5. \u00a0Karpovsky, M.G., K. Kulikowski, and<\/span>Taubin<\/span>,<\/span>“Differential Fault Analysis Attack Resistant Architectures for the Advanced Encryption Standard”<\/a>,\u00a0<\/span>Proc. IFIP World Computing Congress,\u00a0<\/span>Cardis<\/span>,<\/em>\u00a0<\/span>Aug., 2004, pp 177-193<\/li>\n
          6. <\/strong><\/span>Stankovic, R.S.,<\/span>Karpovsky,\u00a0<\/span>M.G., and J.T.\u00a0<\/span>Aastola<\/span>,\u00a0<\/span>“Reduction of the Number of Coefficients in Arithmetic Expressions by Autocorrelation Functions<\/a>“,\u00a0<\/span><\/em>Proc. 2004 International Workshop on Spectral Methods and\u00a0<\/span>Multirate<\/span>\u00a0<\/span>Signal Processing, SMMSP2004<\/em><\/li>\n
          7. Smirnov<\/span>,<\/span>A.Taubin<\/span>,\u00a0<\/span>M.Karpovsky<\/span>\u00a0<\/span>and\u00a0<\/span>L.Rozenblum<\/span>, “Gate Transfer Level Synthesis as an Automated Approach to Fine-Grain Pipelining”<\/a>,\u00a0<\/span>Proc<\/em><\/span>\u00a0<\/span>25th Int. Conference on Application and Theory of Petri Nets,\u00a0<\/span><\/em>2004, pp.67-79.<\/li>\n
          8. Smirnov A., Taubin A., and Karpovsky M.<\/span>“<\/em>Automated Pipelining in ASIC Synthesis Methodology: Gate Transfer Level”<\/em><\/a>,<\/em><\/span> Thirteenth Int. Workshop on Logic and Synthesis,\u00a0<\/span><\/em>2004.<\/li>\n
          9. Stanckovic<\/span>, and<\/span>M.G.Karpovsky<\/span>,\u00a0<\/span>Remarks on Calculation of Autocorrelation on Finite Dyadic Groups by Local Transformations of Decision Diagrams”,\u00a0<\/span><\/a>\u00a0Lecture Notes Springer and\u00a0<\/span>Verlag<\/span><\/em>, 2005<\/li>\n
          10. Kulikowski<\/span>,<\/span>M.Su<\/span>,\u00a0<\/span>A.Smirnov<\/span>,\u00a0<\/span>A.Taubin<\/span>, and\u00a0<\/span>M.G.Karpovsky<\/span>,\u00a0<\/span>D.MacDonald<\/span>, “Delay Insensitive Encoding and Power Analysis: A Balancing Act”,<\/a>\u00a0<\/span>Proc. 11th Int.\u00a0<\/span>Symp<\/span>.\u00a0<\/span>on<\/span>\u00a0<\/span>Asynchronous Circuits and Systems<\/em>, 2005<\/li>\n
          11. .<\/span>Smirnov<\/span>, A. Taubin,<\/span>M.Su<\/span>\u00a0<\/span>and M.G. Karpovsky, “An Automated Fine-Grained Pipelining Using Domino Style Asynchronous Library”<\/a>,\u00a0<\/span>Proc. of ACSD Workshop<\/em>, June 2005<\/li>\n
          12. S.Stankovic<\/span>,<\/span>J.T.Aastola<\/span>\u00a0<\/span>and\u00a0<\/span>M.G.Karpovsky<\/span>, “Remarks on History of Abstract Harmonic Analysis<\/a>“,\u00a0<\/span>Proc. Fifth Int. Workshop on Spectral Methods and Signal Processing, 2005<\/em><\/li>\n
          13. <\/em><\/strong><\/span>M.Mustafa<\/span>,\u00a0<\/span>M.G.Karpovsky<\/span>\u00a0<\/span>and\u00a0<\/span>L.B.Levitin<\/span>, “Cycle Breaking in Wormhole Routed\u00a0 Computer<\/span>\u00a0<\/span>Communication Networks”,\u00a0<\/span>Proc.\u00a0<\/span>Opnetwork<\/span>\u00a0<\/span>, 2005<\/em><\/a><\/li>\n
          14. <\/strong><\/span><\/em>K.J.Kulikowski<\/span>,<\/span>M.G.Karpovsky<\/span>\u00a0<\/span>and\u00a0<\/span>A.Taubin<\/span>, “Robust Codes for Fault Resistant Cryptographic Hardware”,\u00a0<\/span>Proc<\/em><\/span>\u00a0<\/span>of Int. Workshop on Fault Detection and Tolerance in Cryptography<\/em><\/a>,<\/em>\u00a0<\/span>Aug 2005.<\/li>\n
          15. <\/strong><\/span>Karpovsky, M.G., Stankovic, R.S., Moraga, C., \u201dSpectral techniques in binary and multiple-valued switching theory, a review of results in the\u00a0decade 1991-2000<\/a>\u201d,<\/span>Multiple-Valued Logic and Soft Computing,\u00a0<\/span><\/em>Vol. 10, N. 3, 2004, 261-286\u00a0<\/span>\u00a0Levin I., Stankovic R., Karpovsky M., Astola J., (2005) “Construction of Planar BDDs by Using Linearization and Decomposition”,<\/span> of Fourteenth International Workshop on Logic and Synthesis<\/em>, Lake Arrowhead, California, pp. 132-139.<\/li>\n
          16. <\/span><\/strong>F.De<\/span>\u00a0<\/span>Pelegrini<\/span>,\u00a0<\/span>D.Starobinski<\/span>,\u00a0<\/span>M.G.Karpovsky<\/span>,\u00a0<\/span>L.B.Levitin<\/span>, “Scalable Cycle Breaking Algorithms For Gigabit Ethernet Backbones”<\/a>,\u00a0<\/span>Journal of Optical Networking,\u00a0<\/span><\/em>Vol.5, N.1 Jan. 2006, pp.1-23<\/li>\n
          17. Honkala<\/span>,<\/span>M.G.Karpovsky<\/span>,\u00a0<\/span>L.B.Levitin<\/span>, “On Robust and Dynamic Identifying Codes<\/a>“,\u00a0<\/span>IEEE Trans Info Theory<\/em>, Feb 2006, pp599-613<\/li>\n
          18. <\/span><\/strong>K.J.Kulikowski<\/span>,<\/span><\/strong>M.G.Karpovsky<\/span>\u00a0<\/span>and\u00a0<\/span>A.R.Taubin<\/span>, “Power Attacks on Secure Hardware, Based on Early Propagation of Data”,\u00a0<\/span>Int. Workshop on On-Line Testing, pp.131-139\u00a0<\/span><\/em>2006<\/a><\/li>\n
          19. <\/span><\/strong>L.B.L<\/em>evitin<\/span>,<\/span>M.G.Karpovsky<\/span>,\u00a0<\/span>M.Mustafa<\/span>\u00a0<\/span>and\u00a0<\/span>L.Zakrevski<\/span>, “New Algorithm for Finding Cycle-B<\/a>reaking Sets of Turns in a Graph”,\u00a0\u00a0=<\/em><\/span>-98Journal of Graph Algorithms and Applications<\/em>,\u00a0<\/span><\/a>Vol. 10, no. 2, 2006<\/li>\n
          20. <\/strong><\/span>K. J. Kulikowski, M.G. Karpovsky,<\/span>A.Taubin<\/span>,\u00a0<\/span>” DPA<\/span>\u00a0<\/span>on Faulty Cryptographic Hardware and Countermeasures”,<\/a>\u00a0<\/span>Proc<\/em><\/span>\u00a0<\/span>of Int. Workshop on Fault Detection and Tolerance in Cryptography,\u00a0<\/span><\/em>2006<\/li>\n
          21. <\/span><\/strong>G.Gaubatz<\/span>,<\/span>B.Sunar<\/span>,\u00a0<\/span>M.G.Karpovsky<\/span>, “Robust Residue Codes for Fault-Tolerant Public-Key Arithmetic<\/a>“,\u00a0<\/span>Proc<\/em><\/span>\u00a0<\/span>of Int. Workshop on Fault Detection and Tolerance in Cryptography,\u00a0<\/span><\/em>2006<\/li>\n
          22. <\/span><\/strong>Smirnov A., Taubin A., and Karpovsky M., “On Automatic Synthesis of Data Dependent<\/span>Micropipelines<\/span>“\u00a0<\/span>Proc. Int. Workshop on Logic and Synthesis,\u00a0<\/span><\/em>2006<\/li>\n
          23. <\/span><\/strong>I. Levin,<\/span>T<\/em>.\u00a0Keren, G.\u00a0<\/span>Kolotov<\/span>,\u00a0 M.G<\/span>. Karpovsky, “Piece-wise Linearization of Logical Functions<\/a>“\u00a0<\/span>,\u00a0<\/span>Proc<\/span>\u00a0<\/span>Int<\/span>\u00a0<\/span>Workshop on Spectral Techniques, 2006, pp 67-75<\/em><\/li>\n
          24. <\/span><\/strong>R. Stankovic, Jaakko<\/span>\u00a0<\/span>Astola,\u00a0 Mark Karpovsky, “Some remarks on sampling theorem”<\/a>,\u00a0<\/span>Proc<\/em><\/span>\u00a0<\/span>Int<\/span>\u00a0<\/span>Workshop on Spectral Techniques, 2006, pp. 163-171<\/em><\/li>\n
          25. <\/strong><\/span>K. Kulikowski,<\/span>M.G.Karpovsky<\/span>,\u00a0<\/span>A.Taubin<\/span>,”Fault Attack Resistant Cryptographic Hardware with Uniform Error Detection”,\u00a0<\/span>Lecture Notes in Computer Science<\/em>, Springer and\u00a0<\/span>Verlag<\/span>, 2006<\/li>\n
          26. <\/span><\/strong>M.<\/span><\/strong>Mustafa,\u00a0<\/span>L.B.Levitin<\/span>,\u00a0<\/span>M.G.Karpovsky<\/span>, “Weighted Turn Prohibitions in Computer Networks”<\/a>,\u00a0<\/span>Proc.\u00a0<\/span>Opnetwork<\/span>,\u00a0<\/span><\/em>2006<\/li>\n
          27. <\/strong><\/span>G.Gaubatz<\/span>, B. Sunar,<\/span>M.G.Karpovsky<\/span>, “Non-linear Residue Codes for Robust Public-Key Arithmetic”,\u00a0<\/span>Lecture Notes in Computer Science,<\/em>\u00a0<\/span>Vol. 4326\/2006, Fault Diagnosis in Cryptography, pp173-184, 2006<\/li>\n
          28. <\/span><\/strong>Stankovic, R.S. Astola, J., M.G. Karpovsky,<\/span>”\u00a0<\/span>Some Historical Remarks on Switching Theor<\/a>y”,\u00a0<\/span>Proc.Int<\/span>\u00a0<\/span>Workshop on Spectral Techniques,<\/em>\u00a0<\/span>2007<\/li>\n<\/ol>\n
              \n
            1. <\/span><\/strong>K. J. Kulikowski, M. G. Karpovsky,<\/span>A.Taubin<\/span>, “Robust Codes and Robust, Fault Tolerant Architectures of the Advanced Encryption Standard”<\/a>,\u00a0\u00a0Journal<\/em><\/span>\u00a0<\/span>of System Architecture,\u00a0vol. 53, pp138-149,\u00a0<\/span><\/em>2007<\/li>\n<\/ol>\n

              202.M.G.Karpovsky, K. Kulikowski, Z, Wang, “On-Line Self Error Detection with Equal Protection Against All Errors”,<\/em><\/a>\u00a0<\/span>Int. Journal of Highly Reliable Electronic System Design<\/em>, June 2008<\/p>\n

                \n
              1. <\/span><\/strong>K. Kulikowski, V. Venkataraman, Z. Wang, A. Taubin, M.G. Karpovsky, “Asynchronous Balanced Gates Tolerant to Interconnect Variability”<\/a>,<\/span>Proceedings of ISCAS<\/em>, 2008<\/li>\n
              2. <\/strong><\/span>K. Kulikowski, M. G. Karpovsky, A. Taubin, Z. Wang, A.<\/span>Kulikovski<\/span>, “Fault Detection for Secure QDI Asynchronous Circuits<\/a>“,\u00a0<\/span>Proceedings of Workshop on Dependable and Secure\u00a0<\/span>Nanocomputing<\/span><\/em>, DSN-08, 2008<\/li>\n
              3. <\/span><\/strong>K. Kulikowski, Z. Wang, M.G. Karpovsky, “Comparative Analysis of Fault Attack Resistant Architectures for Private and Public Key Cryptosystems<\/a>“,<\/span>Proc<\/em><\/span>\u00a0<\/span>of Int. Workshop on Fault-tolerant Cryptographic Devices<\/em>, 2008<\/li>\n<\/ol>\n

                206.Z.E.Jamous, L. B. Levitin, M. Mustafa, M. G. Karpovsky, “Performance of Cycle-Breaking Algorithms for Deadlock and\u00a0<\/span>Livelock<\/span>\u00a0<\/span>Prevention in Communication Networks”,\u00a0<\/span>Proceedings of\u00a0<\/span>Opnetwork<\/span><\/em>, 2008<\/p>\n

                  \n
                1. \n
                    \n
                  1. <\/span><\/strong>K. Kulikowski, M. G. Karpovsky, “Robust Correction of Repeating Errors by Nonlinear Codes”,<\/span><\/a>\u00a0\u00a0<\/span>Communications<\/em>,\u00a0<\/span>IET,\u00a0<\/span>Vol<\/span>\u00a0<\/span>5 pp2317-2327, 4,\u00a0<\/span><\/em>2011<\/li>\n
                  2. <\/span><\/strong>O.Keren<\/span>, I, Levin, M. G. Karpovsky, “Non-redundant Scheme for Arbitrary Error Detection in Combinational Circuits<\/span>“,<\/a>\u00a0<\/span>Proceedings of 16th IFIP\/IEEE Conference on Very Large Scale Integration<\/em>, 2008<\/li>\n
                  3. <\/strong><\/span>L. Levitin, M. G. Karpovsky, M. Mustafa, “Deadlock prevention by Turn Prohibitions in Interconnection Networks“<\/span><\/a>,\u00a0\u00a0<\/span>Proc. of Int. Workshop on Communication Architecture for Clusters<\/em>, CAC, Rome, May, 2009<\/li>\n
                  4. <\/span><\/em><\/strong>R. S. Stankovic, M. G. Karpovsky, and C. Moraga,<\/span>”\u00a0<\/span>Remarks on Codes, Spectral Transforms, and Decision Diagrams”<\/a>\u00a0 in\u00a0\u00a0<\/span>Tabush<\/span>, I.,\u00a0<\/span>Egiazarian<\/span>, K.,\u00a0<\/span>Gabouj<\/span>, M., (eds.),\u00a0pp 226-246, July,\u00a0<\/span>2009<\/li>\n
                  5. <\/em><\/strong><\/span><\/em>Z. Wang, M. G. Karpovsky, K. Kulikowski,<\/span>“Replacing Linear Hamming Codes by Robust Nonlinear Codes Results in Reliability Improvement for Memories<\/a>“,\u00a0<\/span>Proc. Int.\u00a0<\/span>Symp<\/span>. Dependable Computing<\/em>, July 2009<\/li>\n
                  6. \u00a0Z. Wang, M. G. Karpovsky, B Sunar, “Multilinear Codes for Robust Error Detecrion”,<\/a><\/span><\/span> Int. On-Line Testing<\/span>Symp<\/span>.,<\/span><\/em>\u00a0<\/span>June, 2009<\/li>\n
                  7. S. Baranov, I. Levin,<\/span>Keren<\/span>, M. G. Karpovsky, “Designing Fault Tolerant FSMs by<\/span>Nano<\/span>-PLAs”,\u00a0<\/span>Proc. Int. On-Line Testi<\/em>ng\u00a0<\/span>Symp<\/span>, June 2009<\/li>\n
                  8. <\/span><\/strong>Z. Wang, M. G. Karpovsky, K. Kulikowski,<\/span>“Design of Memories with Concurrent Error Detection and Correction by\u00a0 Non<\/span>-Linear SEC-DED Codes”<\/a>,\u00a0<\/span>Journal of Electronic Testing<\/em>, vol. 26, Oct 2010<\/li>\n
                  9. B. Levitin, M. G. Karpovsky, M. Mustafa, “Minimal Sets of Turns for Breaking Cycles in Graphs Modeling Networks”<\/a><\/span>,\u00a0<\/span>\u00a0IEEE Trans. Parallel and Distributed Systems.<\/em>, vol. 21, No. 9, Sept 2010 , pp. 1342-1353<\/li>\n
                  10. <\/em><\/strong><\/span>Z.<\/span><\/strong>Wang, M.G. Karpovsky,\u00a0<\/span>B.Sunar<\/span>,\u00a0<\/span>A.Joshi<\/span>, “Design of Reliable and Secure Multipliers by\u00a0<\/span>Multilinear<\/span>\u00a0<\/span>Arithmetic Codes”<\/a>,\u00a0<\/span>Proc. Int. Conf. on Information, Communications Security<\/em>, Dec. 2009<\/li>\n
                  11. .<\/em><\/span> Wang, M. G. Karpovsky and A. Joshi, “<\/span>Reliable MLC\u00a0 NAND Flash Memories Based on Non-Linear t-error Correcting Codes”\u00a0<\/span><\/em><\/a>Proc. Int. Conf. on Dependable Systems and Networks,\u00a0<\/span><\/em>June 2010\u00a0<\/span><\/em>\u00a0<\/em><\/a><\/li>\n
                  12. \u00a0Z. Wang, M. Karpovsky,<\/span>“Robust FSMs for Cryptographic Devices Resilient to Strong Fault Injection Attacks”<\/a><\/span>,\u00a0<\/span>Proc<\/em><\/span>\u00a0<\/span>Int<\/span>\u00a0<\/span>Symp<\/span>.\u00a0<\/span>on<\/span>\u00a0<\/span>On-line Testing,<\/em>\u00a0<\/span>July 2010<\/li>\n
                  13. <\/span><\/strong>O. Keren, I. Levin, M. G. Karpovsky,<\/span>“Duplication Based One-to-many Coding for Trojan HW Detection<\/span><\/a>“,\u00a0<\/span>Int.\u00a0<\/span>Symp.on<\/span>\u00a0<\/span>Defect and Fault Tolerance in VLSI Systems<\/em>, 2010<\/li>\n
                  14. <\/span><\/strong>K.D.Akdemir<\/span>, Z. Wang, M. G. Karpovsky, and B. Sunar,\u00a0 “Design of Cryptographic Devices Resilient to Fault Injection Attacks Using Nonlinear Robust Codes<\/a>“,\u00a0<\/span>Fault Analysis in Cryptography,\u00a0<\/span><\/em>M.\u00a0 Joye Editor, 2011\u00a0<\/span>\u00a0<\/em><\/li>\n
                  15. 221.\u00a0<\/span>Wang<\/span>,<\/span>M.G.Karpovsky<\/span>\u00a0<\/span>and\u00a0<\/span>A.Joshi<\/span>,\u00a0 “<\/span>Nonlinear Multi-Error Correcting Codes for Reliable MLC NAND Flash Memories\u00a0\u00a0<\/span><\/a>“,\u00a0\u00a0\u00a0<\/span>IEEE Trans on VLSI<\/em>,\u00a0<\/span>Vol<\/span>\u00a0<\/span>20, No 7, July, 2012, pp. 1221-1235<\/li>\n
                  16. <\/span><\/strong>M. Karpovsky,<\/span>” Design<\/span>\u00a0<\/span>of Secure Hardware Resistant to Attacks”,\u00a0<\/span>Proc. EW Design and Test\u00a0<\/span>Symp<\/span>,<\/em>\u00a0<\/span>Sept 2010<\/li>\n
                  17. <\/span><\/strong>Z. Wang and<\/span>M.G.Karpovsky<\/span>, “Algebraic Manipulation Detection Codes and Their Application for Design of Secure Cryptographic Devices<\/a>“,\u00a0\u00a0Proc<\/em><\/span>\u00a0<\/span>of Int.\u00a0<\/span>Symp<\/span>.\u00a0<\/span>on<\/span>\u00a0<\/span>On-Line Testing<\/em>, 2011<\/li>\n
                  18. \u00a0Wang,<\/span>A.Joshi<\/span>\u00a0<\/span>and\u00a0<\/span>M.G.Karpovsky<\/span>, “Influence of Metallic Tubes on the Reliability of CNTFET SRAMs: Error Mechanisms and Countermeasures”<\/a>,\u00a0<\/span>Proc. GLSVLSI Conference<\/em>,\u00a0 2011<\/span><\/li>\n
                  19. <\/span><\/strong>Z.Wang<\/span>,<\/span>M.G.Karpovsky<\/span>\u00a0<\/span>and\u00a0<\/span>A.Joshi<\/span>,\u00a0\u00a0”\u00a0<\/span>Secure Multipliers Resilient to Strong Fault-Injection Attacks Using\u00a0<\/span>Multilinear<\/span>\u00a0<\/span>Arithmetic Codes<\/a>\u00a0<\/span>“,\u00a0<\/span>IEEE Trans on VLSI,\u00a0<\/span><\/em>Vol<\/span>\u00a0<\/span>20, No 6 , 2012, pp 1036-1049<\/li>\n
                  20. <\/span><\/strong>M.G. Karpovsky and Z. Wang,<\/span>“Design of Strongly Secure Communication and Computation Channels by Nonlinear Error Detecting Codes”,\u00a0\u00a0<\/span>IEEE Trans Computer<\/em>s\u00a0\u00a0<\/span><\/a>\u00a0<\/span>Vol<\/span>\u00a0<\/span>63, No 11, Nov. 2014, pp 2716-2728<\/li>\n
                  21. <\/span>L. Levitin,<\/span>M.G.Karpovsky<\/span>\u00a0<\/span>and M. Mustafa, “Deadlock Prevention in Networks of Workstations with Wormhole Routing<\/a>“,\u00a0<\/span>Distributed Innovations for Business, Engineering and Science,\u00a0\u00a0Edited<\/span><\/em>\u00a0<\/span>by A. Loo,\u00a0<\/span><\/em><\/strong>\u00a02013.<\/li>\n
                  22. <\/span>M.G Karpovsky,<\/span>L.B.Levitin<\/span>, M Mustafa, “Deadlock Prevention in Multiprocessor Systems with Wormhole Routing”<\/a>,\u00a0<\/span>Distributed Innovations for Business, Engineering and Science,\u00a0\u00a0Edited<\/span><\/em>\u00a0<\/span>by A. Loo,\u00a0<\/span><\/em><\/strong>\u00a02013.<\/li>\n
                  23. 229.<\/span>Wang<\/span><\/span>and\u00a0<\/span>M.G.Karpovsky<\/span>, “Reliable and Secure Memories Based on Algebraic Manipulation Correction Codes”<\/a>,\u00a0<\/span>Proc<\/em><\/span>\u00a0<\/span>Int<\/span>\u00a0<\/span>Symp<\/span>.\u00a0<\/span>on<\/span>\u00a0<\/span>On-line Testing,<\/em>\u00a0<\/span>June 2012<\/li>\n
                  24. 230.<\/span>Wang<\/span><\/span>and\u00a0<\/span>M.G.Karpovsky<\/span>,\u00a0<\/span>“New Error Detecting Codes for design of Hardware Resistant to Strong Fault Injection Attacks”<\/a>,\u00a0<\/span>Proc. Int. Conference on Security and Management,\u00a0<\/span>SAM\u00a0,<\/span><\/em>\u00a0<\/span>2012<\/li>\n
                  25. <\/span>P.Luo<\/span>,<\/span>Z.Wang<\/span>\u00a0<\/span>and\u00a0<\/span>M.G.Karpovsky<\/span>, “Secure NAND Flash Memories Resilient to Strong Fault-Injection Attacks Using Algebraic Manipulation Detection Codes”<\/a>,\u00a0<\/span>Proc. Int. Conference\u00a0 on<\/span>\u00a0<\/span>Security and Management, SAM , 2013<\/em><\/li>\n
                  26. <\/span><\/em>Shizun Ge, Zhen Wang, Pei Luo, Mark Karpovsky,<\/span>”\u00a0<\/span>Secure Memories Resistant to Both Random Errors and Fault Injection Attacks Using Nonlinear Error Correction Codes”,<\/a>\u00a0<\/span>Proc. Workshop on Hardware and Architectural Support for Security and Privacy, HASP 2013, 2013<\/em><\/li>\n
                  27. <\/span><\/em>Shizun Ge, Zhen Wang, Pei Luo, Mark Karpovsky, “Reliable and Secure Memories Based on Algebraic Manipulation Detection Codes and Robust Error Correction”\u00a0<\/span><\/a>,\u00a0<\/span>Proc. Int. Depend\u00a0<\/span>Symp<\/span>., 2013<\/em><\/li>\n
                  28. <\/span><\/em>I.<\/span>Shumsky<\/span>,\u00a0<\/span>O.Keren<\/span>,\u00a0<\/span>M.Karpovsky<\/span>, “\u00a0<\/span>Robustness of Security-Oriented Binary Codes Under Non-Uniform Distribution of\u00a0<\/span>Codewords<\/span>“<\/a>,\u00a0<\/span>Proc. Int. Depend\u00a0<\/span>Symp<\/span>.,<\/span>\u00a0<\/span>2013<\/em><\/li>\n
                  29. P. Luo,<\/span>A.Yu-Lun\u00a0<\/span><\/span>Lin, Z. Wang and M.G. Karpovsky, “Hardware Implementation of Reliable and Secure Shamir’s Secret Sharing Scheme”, \u00a0Proc. Int.\u00a0<\/span>Symp<\/span>. On High Assurance Systems Engineering,\u00a0\u00a02014<\/span>.<\/li>\n
                  30. <\/span>M.G. Karpovsky, L. Levitin, M. Mustafa, \u201cOptimal Turn Prohibition for Deadlock Prevention in Networks with Regular Topologies<\/a>\u201d,<\/span>IEEE Trans on Control of Networks,<\/em>\u00a0<\/span>Vol. 1, No 1, March 2014, pp 74-85<\/li>\n
                  31. <\/span>O. Keren, M.G. Karpovsky,<\/span>“Relations between the Entropy of a Source and the Error Masking Probability for Security Oriented Codes<\/a>\u201d,\u00a0<\/span>IEEE Trans on Communications,<\/em>\u00a0<\/span>Vol. 63, No.1, pp206-214, 2015<\/li>\n
                  32. <\/span>Z. Wang, M.G.<\/span>Karpovsky, L. Bu\u00a0<\/span>“Design of Reliable and Secure Devices Realizing Shamir\u2019s Secret Sharing<\/a>\u201d,\u00a0<\/span>IEEE Trans on Computers,<\/em>\u00a0<\/span>Vol.PP<\/span>\u00a0<\/span>, Issue 99, Oct. 2015<\/li>\n
                  33. <\/span>L. Bu, M.G.<\/span>Karpovsky, Z. Wang\u00a0\u00a0<\/span>“New Byte Error Correcting Codes with Simple Decoding for Reliable Cache Design<\/a>\u201d,\u00a0<\/span>Proc. 21st IEEE On-Line Testing Symposium (IOLTS)<\/em>, 2015<\/li>\n
                  34. <\/span>L. Bu, M.G.<\/span>Karpovsky\u00a0\u00a0<\/span>“Protecting Flash Memories with a High Reliability and Low Cost ECC<\/a>“,\u00a0<\/span>International Journal of New Technologies in Science and Engineering<\/em>, vol. 2, Issue. 2, 2015<\/li>\n
                  35. Lake Bu, and M. Karpovsky “A Hybrid Self-Diagnosis Mechanism with Defective Nodes Locating and Attack Detection for Parallel Computing Systems<\/a>“,<\/span>Proc. 22nd IEEE On-Line Testing Symposium (IOLTS)<\/em>, 2016<\/li>\n
                  36. Lake Bu, and M. Karpovsky “A Design of Secure and Reliable Wireless Transmission Channel for Implantable Medical Devices<\/a><\/span>“,\u00a0<\/span>Proc. International Conference on Information Systems Security and Privacy (ICISSP), 2017\u00a0\u00a0<\/span><\/em>[Best Paper Award]<\/li>\n
                  37. Lake Bu, and M. Karpovsky \u201cDesign of reliable storage and compute systems with lightweight group testing based non-binary error correction codes\u201d<\/a>,\u00a0IET\u00a0 Journal of\u00a0Computers & Digital Techniques<\/em>, 2018.<\/li>\n
                  38. \n

                    Lake Bu, M. Karpovsky and M. A. Kinsy\u00a0<\/span>“Bulwark: Securing Implantable Medical Devices Communication Channels<\/a>“,\u00a0Computers and Security,<\/em>\u00a0Elsevier, 2018<\/span><\/p>\n<\/li>\n<\/ol>\n<\/li>\n<\/ol>\n

                     <\/p>\n","protected":false},"excerpt":{"rendered":"

                    Mark Karpovsky Professor Emeritus Boston University. Department of Electrical and Computer Engineering E-mail: markkar@bu.edu Education: Ph.D. Department\u00a0of Mathematics,\u00a0 Leningrad\u00a0Electrotechnical\u00a0Institute, Leningrad, USSR. M.S.\u00a0Department of Computer Science,\u00a0 Leningrad\u00a0Electrotechnical\u00a0Institute, Leningrad, USSR. B.S.\u00a0Department of Computer Science,\u00a0 Leningrad\u00a0Electrotechnical\u00a0Institute, Leningrad, USSR. Employment: June 2002- July. 2002, Visiting Professor, Tampere International Center for Signal Processing. Finland. June 2000- July,\u00a02000, Visiting Professor, Tampere […]<\/p>\n","protected":false},"author":9358,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"_links":{"self":[{"href":"https:\/\/sites.bu.edu\/mark\/wp-json\/wp\/v2\/pages\/56"}],"collection":[{"href":"https:\/\/sites.bu.edu\/mark\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/sites.bu.edu\/mark\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/sites.bu.edu\/mark\/wp-json\/wp\/v2\/users\/9358"}],"replies":[{"embeddable":true,"href":"https:\/\/sites.bu.edu\/mark\/wp-json\/wp\/v2\/comments?post=56"}],"version-history":[{"count":50,"href":"https:\/\/sites.bu.edu\/mark\/wp-json\/wp\/v2\/pages\/56\/revisions"}],"predecessor-version":[{"id":1626,"href":"https:\/\/sites.bu.edu\/mark\/wp-json\/wp\/v2\/pages\/56\/revisions\/1626"}],"wp:attachment":[{"href":"https:\/\/sites.bu.edu\/mark\/wp-json\/wp\/v2\/media?parent=56"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}

            \u00a0200.\u00a0<\/strong>M.G.Karpovsky, K. Kulikowski, Z, Wang, “Robust Error Detection in Communication and Computation Channels”<\/a>,\u00a0<\/span>Keynote paper<\/em><\/strong>, Int. Workshop on Spectral Techniques<\/em>, 2007<\/p>\n

      31. M. G. Karpovsky, “Linear Automata with Error Detection and Error Correction<\/a>” in Monograph:\u00a0<\/span>Using redundancy in Information Systems<\/em>, Prof.\u00a0<\/span>Gelesnov<\/span>\u00a0<\/span>Ed., Leningrad, 1970.<\/p>\n